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1/56 december 2004 m29dw640d 64 mbit (8mb x8 or 4mb x16, multiple bank, page, boot block) 3v supply flash memory features summary supply voltage ?v cc = 2.7v to 3.6v for program, erase and read ?v pp =12v for fast program (optional) asynchronous page read mode ? page width 4 words ? page access 25, 30ns ? random access 70, 90ns programming time ? 10s per byte/word typical ? 4 words / 8 bytes at-a-time program memory blocks ? quadruple bank memory array: 8mbit+24mbit+24mbit+8mbit ? parameter blocks (at both top and bottom) dual operations ? while program or erase in a group of banks (from 1 to 3), read in any of the other banks program/ erase suspend and resume modes ? read from any block during program suspend ? read and program another block during erase suspend unlock bypass program command ? faster production/batch programming v pp /wp pin for fast program and write protect temporary block unprotection mode common flash interface ? 64 bit security code extended memory block ? extra block used as security block or to store additional information figure 1. packages low power consumption ? standby and automatic standby 100,000 program/erase cycles per block electronic signature ? manufacturer code: 0020h ? device code: 227eh + 2202h + 2201h tsop48 (n) 12 x 20mm fbga tfbga63 (za) 7 x 11mm
m29dw640d 2/56 table of contents features summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 1. packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. tsop connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. tfbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. block addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6. block addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 address inputs (a0-a21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 data inputs/outputs (dq0-dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 data inputs/outputs (dq8-dq14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 data input/output or address input (dq15a?1).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 chip enable (e ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 output enable (g ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write enable (w ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 v pp/ write protect (v pp/ wp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 reset/block temporary unprotect (rp ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ready/busy output (rb ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 byte/word organization select (byte ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v cc supply voltage (2.7v to 3.6v).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 v ss ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 automatic standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 electronic signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 block protect and chip unprotect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 3. bus operations, byte = v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. bus operations, byte = v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read/reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 auto select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read cfi query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3/56 m29dw640d program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 fast program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 double word program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 quadruple word program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 double byte program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 quadruple byte program command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 octuple byte program command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 unlock bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 unlock bypass program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 unlock bypass reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 chip erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 program suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 program resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 enter extended block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 exit extended block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 block protect and chip unprotect commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. commands, 16-bit mode, byte = v ih . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 6. commands, 8-bit mode, byte = v il . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 7. program, erase times and program, erase endurance cycles . . . . . . . . . . . . . . . . . . . 22 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 data polling bit (dq7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 toggle bit (dq6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 error bit (dq5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 erase timer bit (dq3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 alternative toggle bit (dq2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 7. data polling flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8. toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9. dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 10. dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 12. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 9. ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 10.ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 13. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 14. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
m29dw640d 4/56 figure 11.random read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12.page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 15. read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 13.write ac waveforms, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 16. write ac characteristics, write enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 14.write ac waveforms, chip enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 17. write ac characteristics, chip enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 15.toggle and alternative toggle bits mechanism, chip enable controlled . . . . . . . . . . . . 34 figure 16.toggle and alternative toggle bits mechanism, output enable controlled . . . . . . . . . . 34 table 18. toggle and alternative toggle bits ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 17.reset/block temporary unprotect ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 19. reset/block temporary unprotect ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 18.accelerated program timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 19.tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package outline. . . . . . . . . 36 table 20. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package mechanical data . 36 figure 20.tfbga63 7x11mm - 6x8 active ball array, 0.8mm pitch, package outline. . . . . . . . . . . 37 table 21. tfbga63 7x11mm - 6x8 active ball array, 0.8mm pitch, package mechanical data . . . 37 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 22. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 appendix a.block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 9 table 23. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 appendix b.common flash interface (cfi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 24. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 25. cfi query identification string. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 table 26. cfi query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 27. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 table 28. primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 29. security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 appendix c.extended memory block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 factory locked extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 customer lockable extended block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 30. extended block address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 appendix d.block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 in-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 31. programmer technique bus operations, byte = v ih or v il . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 21.programmer equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 22.programmer equipment chip unprotect flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
5/56 m29dw640d figure 23.in-system equipment group protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 24.in-system equipment chip unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 32. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
m29dw640d 6/56 summary description the m29dw640d is a 64 mbit (8mb x8 or 4mb x16) non-volatile memory that can be read, erased and reprogrammed. these operations can be per- formed using a single low voltage (2.7 to 3.6v) supply. on power-up the memory defaults to its read mode. the device features an asymmetrical block archi- tecture, with 16 parameter and 126 main blocks, divided into four banks, a, b, c and d, providing multiple bank operations. while programming or erasing is underway in one group of banks (from 1 to 3), reading can be conducted in any of the other banks. the bank architecture is summarized in ta- ble 2 . eight of the parameter blocks are at the top of the memory address space, and eight are at the bottom. the m29dw640d has one extra 256 byte block (extended block) that can be accessed using a dedicated command. the extended block can be protected and so is useful for storing security infor- mation. however the protection is irreversible, once protected the protection cannot be undone. each block can be erased independently, so it is possible to preserve valid data while old data is erased. the blocks can be protected to prevent accidental program or erase commands from modifying the memory. program and erase com- mands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special op- erations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identi- fied. the command set required to control the memory is consistent with jedec standards. chip enable, output enable and write enable sig- nals control the bus operation of the memory. they allow simple connection to most micropro- cessors, often without additional logic. the memory is offered in tsop48 (12x20mm) and tfbga63 (7x11mm, 0.8mm pitch) packages. the memory is supplied with all the bits erased (set to ?1?). figure 2. logic diagram table 1. signal names ai06877b 22 a0-a21 w dq0-dq14 v cc m29dw640d e v ss 15 g rp dq15a?1 rb v pp /wp byte a0-a21 address inputs dq0-dq7 data inputs/outputs dq8-dq14 data inputs/outputs dq15a?1 data input/output or address input e chip enable g output enable w write enable rp reset/block temporary unprotect rb ready/busy output byte byte/word organization select v cc supply voltage v pp /wp v pp /write protect v ss ground nc not connected internally
7/56 m29dw640d figure 3. tsop connections dq3 dq9 dq2 a6 dq0 w a3 rb dq6 a8 a9 dq13 a17 a10 dq14 a2 dq12 dq10 dq15a?1 v cc dq4 dq5 a7 dq7 v pp /wp a21 ai06878b m29dw640d 12 1 13 24 25 36 37 48 dq8 a20 a19 a1 a18 a4 a5 dq1 dq11 g a12 a13 a16 a11 byte a15 a14 v ss e a0 rp v ss
m29dw640d 8/56 figure 4. tfbga connections (top view through package) note: 1. balls are shorted together via the substrate but not connected to the die. 6 5 4 3 2 1 v ss a15 a14 a12 a13 dq3 dq11 dq10 a18 v pp / wp rb dq1 dq9 dq8 dq0 a6 a17 a7 g e a0 a4 a3 dq2 dq6 dq13 dq14 a10 a8 a9 dq4 v cc dq12 dq5 a19 a21 rp w a11 dq7 a1 a2 v ss a5 a20 a16 byte c b a e d f g h dq15 a?1 nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) nc (1) j k l m 8 7 nc (1) nc (1) nc (1) nc (1) ai06879
9/56 m29dw640d table 2. bank architecture figure 5. block addresses (x8) note: also see appendix a , table 23 for a full listing of the block addresses. bank bank size parameter blocks main blocks no. of blocks block size no. of blocks block size a 8 mbit 8 8kbyte/ 4 kword 15 64kbyte/ 32 kword b 24 mbit ? ? 48 64kbyte/ 32 kword c 24 mbit ? ? 48 64kbyte/ 32 kword d 8 mbit 8 8kbyte/ 4 kword 15 64kbyte/ 32 kword ai06880 64 kbyte or 32 kword 400000h 40ffffh 64 kbyte or 32 kword 7e0000h 7effffh (x8) address lines a21-a0, dq15a-1 64 kbyte or 32 kword 6f0000h 6fffffh total of 48 main blocks 64 kbyte or 32 kword 700000h 70ffffh 8 kbyte or 4 kword 7fe000h 7fffffh 8 kbyte or 4 kword 7f0000h 7f1fffh total of 15 main blocks total of 8 parameter blocks bank c bank d 8 kbyte or 4 kword 000000h 001fffh 64 kbyte or 32 kword 0f0000h 0fffffh 8 kbyte or 4 kword 00e000h 00ffffh total of 8 parameter blocks 64 kbyte or 32 kword 010000h 01ffffh 64 kbyte or 32 kword 3f0000h 3fffffh 64 kbyte or 32 kword 100000h 10ffffh total of 15 main blocks total of 48 main blocks bank b bank a
m29dw640d 10/56 figure 6. block addresses (x16) note: also see appendix a , table 23 for a full listing of the block addresses. ai05555 64 kbyte or 32 kword 200000h 207fffh 64 kbyte or 32 kword 3f0000h 3f7fffh (x16) address lines a21-a0 64 kbyte or 32 kword 378000h 37ffffh total of 48 main blocks 64 kbyte or 32 kword 380000h 387fffh 8 kbyte or 4 kword 3ff000h 3fffffh 8 kbyte or 4 kword 3f8000h 3f8fffh total of 15 main blocks total of 8 parameter blocks bank c bank d 8 kbyte or 4 kword 000000h 000fffh 64 kbyte or 32 kword 078000h 07ffffh 8 kbyte or 4 kword 007000h 007fffh total of 8 parameter blocks 64 kbyte or 32 kword 008000h 00ffffh 64 kbyte or 32 kword 1f8000h 1fffffh 64 kbyte or 32 kword 080000h 087fffh total of 15 main blocks total of 48 main blocks bank b bank a
11/56 m29dw640d signal descriptions see figure 2., logic diagram , and table 1., signal names , for a brief overview of the sig- nals connected to this device. address inputs (a0-a21). the address inputs select the cells in the memory array to access dur- ing bus read operations. during bus write opera- tions they control the commands sent to the command interface of the internal state machine. data inputs/outputs (dq0-dq7). the data i/o outputs the data stored at the selected address during a bus read operation. during bus write operations they represent the commands sent to the command interface of the internal state ma- chine. data inputs/outputs (dq8-dq14). the data i/o outputs the data stored at the selected address during a bus read operation when byte is high, v ih . when byte is low, v il , these pins are not used and are high impedance. during bus write operations the command register does not use these bits. when reading the status register these bits should be ignored. data input/output or address input (dq15a?1). when byte is high, v ih , this pin behaves as a data input/output pin (as dq8-dq14). when byte is low, v il , this pin behaves as an address pin; dq15a?1 low will select the lsb of the ad- dressed word, dq15a?1 high will select the msb. throughout the text consider references to the data input/output to include this pin when byte is high and references to the address inputs to in- clude this pin when byte is low except when stated explicitly otherwise. chip enable (e ). the chip enable, e , activates the memory, allowing bus read and bus write op- erations to be performed. when chip enable is high, v ih , all other pins are ignored. output enable (g ). the output enable, g , con- trols the bus read operation of the memory. write enable (w ). the write enable, w , controls the bus write operation of the memory?s com- mand interface. v pp/ write protect (v pp /wp ). the v pp /write protect pin provides two functions. the v pp func- tion allows the memory to use an external high voltage power supply to reduce the time required for program operations. this is achieved by by- passing the unlock cycles and/or using the multi- ple word (2 or 4 at-a-time) or multiple byte program (2, 4 or 8 at-a-time) commands. the write protect function provides a hardware meth- od of protecting the four outermost boot blocks (two at the top, and two at the bottom of the ad- dress space). when v pp /write protect is low, v il , the memory protects the four outermost boot blocks; program and erase operations in these blocks are ignored while v pp /write protect is low, even when rp is at v id . when v pp /write protect is high, v ih , the memory reverts to the previous protection status of the four outermost boot blocks (two at the top, and two at the bottom of the address space). program and erase operations can now modify the data in these blocks unless the blocks are protected using block protection. when v pp /write protect is raised to v pp the mem- ory automatically enters the unlock bypass mode. when v pp /write protect returns to v ih or v il nor- mal operation resumes. during unlock bypass program operations the memory draws i pp from the pin to supply the programming circuits. see the description of the unlock bypass command in the command interface section. the transitions from v ih to v pp and from v pp to v ih must be slower than t vhvpp , see figure 18 . never raise v pp /write protect to v pp from any mode except read mode, otherwise the memory may be left in an indeterminate state. the v pp /write protect pin must not be left floating or unconnected or the device may become unreli- able. a 0.1f capacitor should be connected be- tween the v pp /write protect pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during unlock bypass program, i pp . reset/block temporary unprotect (rp ). the reset/block temporary unprotect pin can be used to apply a hardware reset to the memory or to temporarily unprotect all blocks that have been protected. note that if v pp /wp is at v il , then the four outer- most boot blocks will remain protected even if rp is at v id . a hardware reset is achieved by holding reset/ block temporary unprotect low, v il , for at least t plpx . after reset/block temporary unprotect goes high, v ih , the memory will be ready for bus read and bus write operations after t phel or t rhel , whichever occurs last. see the ready/busy output section, table 19 and figure 17., reset/ block temporary unprotect ac waveforms . holding rp at v id will temporarily unprotect the protected blocks in the memory. program and erase operations on all blocks will be possible. the transition from v ih to v id must be slower than t phphh .
m29dw640d 12/56 ready/busy output (rb ). the ready/busy pin is an open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations ready/busy is low, v ol . ready/busy is high-im- pedance during read mode, auto select mode and erase suspend mode. after a hardware reset, bus read and bus write operations cannot begin until ready/busy be- comes high-impedance. see table 19 and figure 17., reset/block temporary unprotect ac wave- forms . the use of an open-drain output allows the ready/ busy pins from several memories to be connected to a single pull-up resistor. a low will then indicate that one, or more, of the memories is busy. byte/word organization select (byte ). the byte/word organization select pin is used to switch between the x8 and x16 bus modes of the memory. when byte/word organization select is low, v il , the memory is in x8 mode, when it is high, v ih , the memory is in x16 mode. v cc supply voltage (2.7v to 3.6v). v cc pro- vides the power supply for all operations (read, program and erase). the command interface is disabled when the v cc supply voltage is less than the lockout voltage, v lko . this prevents bus write operations from ac- cidentally damaging the data during power up, power down and power surges. if the program/ erase controller is programming or erasing during this time then the operation aborts and the memo- ry contents being altered will be invalid. a 0.1f capacitor should be connected between the v cc supply voltage pin and the v ss ground pin to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations, i cc3 . v ss ground. v ss is the reference for all voltage measurements. the device features two v ss pins both of which must be connected to the system ground.
13/56 m29dw640d bus operations there are five standard bus operations that control the device. these are bus read (random and page modes), bus write, output disable, standby and automatic standby. using the multiple bank architecture of the m29dw640d, while programming or erasing is underway in one group of banks (from 1 to 3), reading can be conducted in any of the other banks. write operations are only allowed in one bank at a time. see tables 3 and 4 , bus operations, for a summa- ry. typically glitches of less than 5ns on chip en- able, write enable, and reset pins are ignored by the memory and do not affect bus operations. bus read. bus read operations read from the memory cells, or specific registers in the com- mand interface. to speed up the read operation the memory array can be read in page mode where data is internally read and stored in a page buffer. the page has a size of 4 words and is ad- dressed by the address inputs a0-a1. a valid bus read operation involves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable high, v ih . the data in- puts/outputs will output the value, see figure 11., random read ac waveforms , figure 12., page read ac waveforms , and table 15., read ac characteristics , for details of when the output becomes valid. bus write. bus write operations write to the command interface. a valid bus write operation begins by setting the desired address on the ad- dress inputs. the address inputs are latched by the command interface on the falling edge of chip enable or write enable, whichever occurs last. the data inputs/outputs are latched by the com- mand interface on the rising edge of chip enable or write enable, whichever occurs first. output en- able must remain high, v ih , during the whole bus write operation. see figures 13 and 14 , write ac waveforms, and tables 16 and 17 , write ac characteristics, for details of the timing require- ments. output disable. the data inputs/outputs are in the high impedance state when output enable is high, v ih . standby. when chip enable is high, v ih , the memory enters standby mode and the data in- puts/outputs pins are placed in the high-imped- ance state. to reduce the supply current to the standby supply current, i cc2 , chip enable should be held within v cc 0.2v. for the standby current level see table 14., dc characteristics . during program or erase operations the memory will continue to use the program/erase supply current, i cc3 , for program or erase operations un- til the operation completes. automatic standby. if cmos levels (v cc 0.2v) are used to drive the bus and the bus is inactive for 300ns or more the memory enters automatic standby where the internal supply current is re- duced to the standby supply current, i cc2 . the data inputs/outputs will still output data if a bus read operation is in progress. special bus operations additional bus operations can be performed to read the electronic signature and also to apply and remove block protection. these bus opera- tions are intended for use by programming equip- ment and are not usually used in applications. they require v id to be applied to some pins. electronic signature. the memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. these codes can be read by applying the signals listed in tables 3 and 4 , bus operations. block protect and chip unprotect. groups of blocks can be protected against accidental pro- gram or erase. the protection groups are shown in appendix a , table 23., block addresses the whole chip can be unprotected to allow the data in- side the blocks to be changed. the v pp /write protect pin can be used to protect the four outermost boot blocks. when v pp /write protect is at v il the four outermost boot blocks are protected and remain protected regardless of the block protection status or the reset/block temporary unprotect pin status. block protect and chip unprotect operations are described in appendix d .
m29dw640d 14/56 table 3. bus operations, byte = v il note: x = v il or v ih . table 4. bus operations, byte = v ih note: x = v il or v ih . operation e g w address inputs data inputs/outputs a21- a12 a3 a2 a1 a0 others, dq15a-1 dq14 -dq8 dq7-dq0 bus read v il v il v ih cell address hi-z data output bus write v il v ih v il command address hi-z data input output disable x v ih v ih x hi-z hi-z standby v ih x x x hi-z hi-z read manufacturer code v il v il v ih bank addrs v il v il v il v il a6 = v il a9 = v id , others =x hi-z 20h read device code (cycle 1) v il v il v ih v il v il v il v ih hi-z 7eh read device code (cycle 2) v il v il v ih v ih v ih v ih v il hi-z 02h read device code (cycle 3) v il v il v ih v ih v ih v ih v ih hi-z 01h extended block indicator bit (dq7) v il v il v ih bank a v il v il v ih v ih hi-z 80h (factory locked) 00h (not locked) block protection verification v il v il v ih block addrs v il v il v ih v il hi-z 01h (protected) 00h (unprotected) operation e g w address inputs data inputs/outputs a21- a12 a3 a2 a1 a0 others dq15a-1, dq14-dq0 bus read v il v il v ih cell address data output bus write v il v ih v il command address data input output disable x v ih v ih xhi-z standby v ih xx x hi-z read manufacturer code v il v il v ih bank addrs v il v il v il v il a6 = v il a9 = v id , others =x 0020h read device code (cycle 1) v il v il v ih v il v il v il v ih 227eh read device code (cycle 2) v il v il v ih v ih v ih v ih v il 2202h read device code (cycle 3) v il v il v ih v ih v ih v ih v ih 2201h extended block indicator bit (dq7) v il v il v ih bank a v il v il v ih v ih 0080h (factory locked) 0000h (not locked) block protection verification v il v il v ih block addrs v il v il v ih v il 0001h (protected) 0000h (unprotected)
15/56 m29dw640d command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. failure to observe a valid sequence of bus write operations will result in the memory return- ing to read mode. the long command sequences are imposed to maximize data security. the address used for the commands changes de- pending on whether the memory is in 16-bit or 8- bit mode. see either table 5 , or 6 , depending on the configuration that is being used, for a summary of the commands. read/reset command the read/reset command returns the memory to its read mode. it also resets the errors in the sta- tus register. either one or three bus write opera- tions can be used to issue the read/reset command. the read/reset command can be issued, be- tween bus write cycles before the start of a pro- gram or erase operation, to return the device to read mode. if the read/reset command is issued during the timeout of a block erase operation then the memory will take up to 10s to abort. during the abort period no valid data can be read from the memory. the read/reset command will not abort an erase operation when issued while in erase suspend. auto select command the auto select command is used to read the manufacturer code and device code, the block protection status and the extended block indica- tor. it can be addressed to either bank. three con- secutive bus write operations are required to issue the auto select command. the final write cycle must be addressed to one of the banks. once the auto select command is issued bus read operations to the bank where the command was issued output the auto select data. bus read operations to the other bank will output the con- tents of the memory array. the memory remains in auto select mode until a read/reset or cfi query command is issued. this command must be is- sued addressing the same bank, as was given when entering auto select mode. in auto select mode the manufacturer code can be read using a read operation, a6 and a3 to a0 each held at v il , and a21-a19 set to the bank ad- dress. the other address bits may be set to either v il or v ih . the device codes can be read using a read oper- ation, a6 held at v il , a3 to a0 each held at the lev- els given in tables 3 and 4 , and a21-a19 set to the bank address. the other address bits may be set to either v il or v ih . the block protection status of each block can be read using a read operation, a6 a3 a2 a0 each held at v il , a1 held at v ih , and a21-a19 set to the bank address, and a18-a12 specifying the ad- dress of the block inside the bank. the other ad- dress bits may be set to either v il or v ih . if the addressed block is protected then 01h is output on data inputs/outputs dq0-dq7, otherwise 00h is output. the extended block status of the extended block can be read using a read operation, a6, a3 and a2, at v il , a0 and a1, at v ih , and a21-a19 set to bank address a. the other bits may be set to ei- ther v il or v ih (don't care). if the extended block is "factory locked" then 80h is output on data in- put/outputs dq0-dq7, otherwise 00h is output. read cfi query command the read cfi query command is used to put the addressed bank in read cfi query mode. once in read cfi query mode bus read operations to the same bank will output data from the common flash interface (cfi) memory area. if the read op- erations are to a different bank from the one spec- ified in the command then the read operations will output the contents of the memory array and not the cfi data. one bus write cycle is required to issue the read cfi query command. care must be taken to issue the command to one of the banks (a21-a19) along with the address shown in tables 3 and 4 (a-1, a0-a10). once the command is issued subse- quent bus read operations in the same bank (a21-a19) to the addresses shown in appendix b (a7-a0), will read from the common flash inter- face memory area. this command is valid only when the device is in the read array or autoselected mode. to enter read cfi query mode from auto select mode, the read cfi query command must be issued to the same bank address as the auto select command, otherwise the device will not enter read cfi que- ry mode. the read/reset command must be issued to re- turn the device to the previous mode (the read ar- ray mode or autoselected mode). a second read/ reset command would be needed if the device is to be put in the read array mode from autoselect- ed mode. see appendix b , tables 24 , 25 , 26 , 27 , 28 and 29 for details on the information contained in the common flash interface (cfi) memory area.
m29dw640d 16/56 program command the program command can be used to program a value to one address in the memory array at a time. the command requires four bus write oper- ations, the final write operation latches the ad- dress and data in the internal state machine and starts the program/erase controller. programming can be suspended and then re- sumed by issuing a program suspend command and a program resume command, respectively (see program suspend command and program resume command paragraphs). if the address falls in a protected block then the program command is ignored, the data remains unchanged. the status register is never read and no error condition is given. after programming has started, bus read opera- tions in the bank being programmed output the status register content, while bus read opera- tions to the other bank output the contents of the memory array. see the section on the status reg- ister for more details. typical program times are given in table 7 . after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs bus read operations to the bank where the command was issued will continue to output the status reg- ister. a read/reset command must be issued to reset the error condition and return to read mode. note that the program command cannot change a bit set at ?0? back to ?1?. one of the erase com- mands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. fast program commands there are five fast program commands available to improve the programming throughput, by writing several adjacent words or bytes in parallel. double word program command. this is used to write two adjacent words in x16 mode, in parallel. the addresses of the two words must dif- fer only in a0. three bus write cycles are necessary to issue the command. the first bus cycle sets up the command. the second bus cycle latches the address and the data of the first word to be written. the third bus cycle latches the address and the data of the second word to be written and starts the program/erase controller. quadruple word program command. this is used to write a page of four adjacent words, in x16 mode, in parallel. the addresses of the four words must differ only in a1 and a0. five bus write cycles are necessary to issue the command. the first bus cycle sets up the command. the second bus cycle latches the address and the data of the first word to be written. the third bus cycle latches the address and the data of the second word to be written. the fourth bus cycle latches the address and the data of the third word to be written. the fifth bus cycle latches the address and the data of the fourth word to be written and starts the program/erase controller. double byte program command. this is used to write two adjacent bytes in x8 mode, in parallel. the addresses of the two bytes must differ only in dq15a-1. three bus write cycles are necessary to issue the command. the first bus cycle sets up the command. the second bus cycle latches the address and the data of the first byte to be written. the third bus cycle latches the address and the data of the second byte to be written and starts the program/erase controller. quadruple byte program command. this is used to write four adjacent bytes in x8 mode, in parallel. the addresses of the four bytes must dif- fer only in a0, dq15a-1. five bus write cycles are necessary to issue the command. the first bus cycle sets up the command. the second bus cycle latches the address and the data of the first byte to be written. the third bus cycle latches the address and the data of the second byte to be written. the fourth bus cycle latches the address and the data of the third byte to be written. the fifth bus cycle latches the address and the data of the fourth byte to be written and starts the program/erase controller. octuple byte program command. this is used to write eight adjacent bytes, in x8 mode, in paral- lel. the addresses of the eight bytes must differ only in a1, a0 and dq15a-1. nine bus write cycles are necessary to issue the command. the first bus cycle sets up the command. the second bus cycle latches the address and the data of the first byte to be written. the third bus cycle latches the address and the data of the second byte to be written. the fourth bus cycle latches the address and the data of the third byte to be written.
17/56 m29dw640d the fifth bus cycle latches the address and the data of the fourth byte to be written. the sixth bus cycle latches the address and the data of the fifth byte to be written. the seventh bus cycle latches the address and the data of the sixth byte to be written. the eighth bus cycle latches the address and the data of the seventh byte to be written. the ninth bus cycle latches the address and the data of the eighth byte to be written and starts the program/erase controller. only one bank can be programmed at any one time. the other bank must be in read mode or erase suspend. fast programming should not be attempted when v pp is not at v pph . after programming has started, bus read opera- tions in the bank being programmed output the status register content, while bus read opera- tions to the other bank output the contents of the memory array. programming can be suspended and then re- sumed by issuing a program suspend command and a program resume command, respectively. (see program suspend command and program resume command paragraphs.) after the program operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs bus read operations to the bank where the command was issued will continue to output the status reg- ister. a read/reset command must be issued to reset the error condition and return to read mode. note that the fast program commands cannot change a bit set at ?0? back to ?1?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. typical program times are given in table 7., program, erase times and program, erase endurance cycles . unlock bypass command the unlock bypass command is used in conjunc- tion with the unlock bypass program command to program the memory faster than with the standard program commands. when the cycle time to the device is long, considerable time saving can be made by using these commands. three bus write operations are required to issue the unlock by- pass command. once the unlock bypass command has been is- sued the bank enters unlock bypass mode. the unlock bypass program command can then be is- sued to program addresses within the bank, or the unlock bypass reset command can be issued to return the bank to read mode. in unlock bypass mode the memory can be read as if in read mode. when v pp is applied to the v pp /write protect pin the memory automatically enters the unlock by- pass mode and the unlock bypass program com- mand can be issued immediately. unlock bypass program command the unlock bypass program command can be used to program one address in the memory array at a time. the command requires two bus write operations, the final write operation latches the ad- dress and data in the internal state machine and starts the program/erase controller. the program operation using the unlock bypass program command behaves identically to the pro- gram operation using the program command. the operation cannot be aborted, a bus read opera- tion to the bank where the command was issued outputs the status register. see the program command for details on the behavior. unlock bypass reset command the unlock bypass reset command can be used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the unlock bypass reset command. read/ reset command does not exit from unlock bypass mode. chip erase command the chip erase command can be used to erase the entire chip. six bus write operations are re- quired to issue the chip erase command and start the program/erase controller. if any blocks are protected then these are ignored and all the other blocks are erased. if all of the blocks are protected the chip erase operation ap- pears to start but will terminate within about 100s, leaving the data unchanged. no error condition is given when protected blocks are ignored. during the erase operation the memory will ignore all commands, including the erase suspend com- mand. it is not possible to issue any command to abort the operation. typical chip erase times are given in table 7 . all bus read operations during the chip erase operation will output the status register on the data inputs/outputs. see the sec- tion on the status register for more details. after the chip erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs the memory will continue to output the status regis- ter. a read/reset command must be issued to re- set the error condition and return to read mode. the chip erase command sets all of the bits in un- protected blocks of the memory to ?1?. all previous data is lost.
m29dw640d 18/56 block erase command the block erase command can be used to erase a list of one or more blocks in one or more banks. it sets all of the bits in the unprotected selected blocks to ?1?. all previous data in the selected blocks is lost. six bus write operations are required to select the first block in the list. each additional block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. the block erase operation starts the pro- gram/erase controller after a time-out period of 50s after the last bus write operation. once the program/erase controller starts it is not possible to select any more blocks. each additional block must therefore be selected within 50s of the last block. the 50s timer restarts when an additional block is selected. after the sixth bus write opera- tion a bus read operation within the same bank will output the status register. see the status register section for details on how to identify if the program/erase controller has started the block erase operation. if any selected blocks are protected then these are ignored and all the other selected blocks are erased. if all of the selected blocks are protected the block erase operation appears to start but will terminate within about 100s, leaving the data un- changed. no error condition is given when protect- ed blocks are ignored. during the block erase operation the memory will ignore all commands except the erase suspend command and the read/reset command which is only accepted during the 50s time-out period. typical block erase times are given in table 7 . after the erase operation has started all bus read operations to the banks being erased will output the status register on the data inputs/outputs. see the section on the status register for more details. after the block erase operation has completed the memory will return to the read mode, unless an error has occurred. when an error occurs bus read operations to the banks where the com- mand was issued will continue to output the status register. a read/reset command must be issued to reset the error condition and return to read mode. erase suspend command the erase suspend command may be used to temporarily suspend a block or multiple block erase operation. one bus write operation specify- ing the bank address of one of the blocks being erased is required to issue the command. issuing the erase suspend command returns the whole device to read mode. the program/erase controller will suspend within the erase suspend latency time (see table 7 for value) of the erase suspend command being is- sued. once the program/erase controller has stopped the memory will be set to read mode and the erase will be suspended. if the erase suspend command is issued during the period when the memory is waiting for an additional block (before the program/erase controller starts) then the erase is suspended immediately and will start im- mediately when the erase resume command is issued. it is not possible to select any further blocks to erase after the erase resume. during erase suspend it is possible to read and program cells in blocks that are not being erased; both read and program operations behave as normal on these blocks. if any attempt is made to program in a protected block or in the suspended block then the program command is ignored and the data remains unchanged. the status register is not read and no error condition is given. read- ing from blocks that are being erased will output the status register. it is also possible to issue the auto select, read cfi query and unlock bypass commands during an erase suspend. the read/reset command must be issued to return the device to read array mode before the resume command will be ac- cepted. during erase suspend a bus read operation to the extended block will output the extended block data. once in the extended block mode, the exit extended block command must be issued before the erase operation can be resumed. erase resume command the erase resume command is used to restart the program/erase controller after an erase sus- pend. the command must include the bank ad- dress of the erase-suspended bank, otherwise the program/erase controller is not restarted. the device must be in read array mode before the resume command will be accepted. an erase can be suspended and resumed more than once. program suspend command the program suspend command allows the sys- tem to interrupt a program operation so that data can be read from any block. when the program suspend command is issued during a program op- eration, the device suspends the program opera- tion within the program suspend latency time (see table 7 for value) and updates the status register bits. the bank addresses of the block being programmed must be specified in the pro- gram suspend command. after the program operation has been suspended, the system can read array data from any address.
19/56 m29dw640d however, data read from program-suspended ad- dresses is not valid. the program suspend command may also be is- sued during a program operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the extended block area (one-time program area), the user must use the proper command sequences to enter and exit this region. the system may also issue the auto select com- mand sequence when the device is in the program suspend mode. the system can read as many auto select codes as required. when the device exits the auto select mode, the device reverts to the program suspend mode, and is ready for an- other valid operation. see auto select command sequence for more information. program resume command after the program resume command is issued, the device reverts to programming. the controller can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write operation status for more information. the system must write the program resume com- mand, specifying the bank addresses of the pro- gram-suspended block, to exit the program suspend mode and to continue the programming operation. further issuing of the resume command is ig- nored. another program suspend command can be written after the device has resumed program- ming. enter extended block command the m29dw640d has one extra 256-byte block (extended block) that can only be accessed using the enter extended block command. three bus write cycles are required to issue the extended block command. once the command has been is- sued the device enters extended block mode where all bus read or program operations to the 000000h-00007fh (word) or 000000h-0000ffh (byte) addresses access the extended block. the extended block cannot be erased, and can be treated as one-time programmable (otp) memo- ry. in extended block mode only array cell loca- tions (bank a) with the same addresses as the extended block (000000h-00007fh (word) or 000000h-0000ffh (byte)) are not accessible. in extended block mode dual operations are allowed and the extended block physically belongs to bank a. when in extended block mode, erase, chip erase, erase suspend and erase resume com- mands are not allowed. to exit from the extended block mode the exit ex- tended block command must be issued. the extended block can be protected, however once protected the protection cannot be undone. exit extended block command the exit extended block command is used to exit from the extended block mode and return the de- vice to read mode. four bus write operations are required to issue the command. block protect and chip unprotect commands groups of blocks can be protected against acci- dental program or erase. the protection groups are shown in appendix a , table 23., block ad- dresses . the whole chip can be unprotected to al- low the data inside the blocks to be changed. block protect and chip unprotect operations are described in appendix d .
m29dw640d 20/56 table 5. commands, 16-bit mode, byte = v ih note: 1. x don?t care, pa program address, pd program data, ba any address in the block, bka bank address. all values in the tabl e are in hexadecimal. 2. normally the command interface only uses a?1, a0-a10 and dq0- dq7 to verify the commands and a11-a21 are don?t care, how- ever for the read cfi command a21-a14 must specify a bank address, and the subsequent read operations must be addressed to the same bank. command length bus write operations 1st 2nd 3rd 4th 5th 6th add data add data add data add data add data add data read/reset 1x f0 3555 aa2aa55 x f0 auto select 3 555 aa 2aa 55 (bka) 555 90 program 4 555 aa 2aa 55 555 a0 pa pd double word program 3 555 50 pa0 pd0 pa1 pd1 quadruple word program 3 555 56 pa0 pd0 pa1 pd1 pa2 pd2 pa3 pd3 unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program 2 x a0 pa pd unlock bypass reset 2 x 90 x 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 block erase 6+ 555 aa 2aa 55 555 80 555 aa 2aa 55 ba 30 erase/program suspend 1 bka b0 erase/program resume 1 bka 30 read cfi query (2) 1 (bka) 55 98 enter extended block 3 555 aa 2aa 55 555 88 exit extended block 4 555 aa 2aa 55 555 90 x 00
21/56 m29dw640d table 6. commands, 8-bit mode, byte = v il note: 1. x don?t care, pa program address, pd program data, ba an y address in the block. all values in the table are in hexadecim al. 2. normally the command interface only uses a?1, a0-a10 and dq0- dq7 to verify the commands and a11-a21 are don?t care, how- ever for the read cfi command a21-a14 must specify a bank address, and the subsequent read operations must be addressed to the same bank. command length bus write operations 1st 2nd 3rd 4th 5th 6th 7th 8th 9th add data add data add data add data add data add data add data add data add data read/reset 1x f0 3aaa aa55555 x f0 auto select 3 aaa aa 555 55 (bka) aaa 90 program 4 aaa aa 555 55 aaa a0 pa pd double byte program 3 aaa 50 pa0 pd1 pa1 pd1 quadruple byte program 5 aaa 56 pa0 pd0 pa1 pd1 pa2 pd2 pa3 pd3 octuple byte program 5 aaa 8b pa0 pd0 pa1 pd1 pa2 pd2 pa3 pd3 pa4 pd4 pa5 pd5 pa6 pd6 pa7 pd7 unlock bypass 3 aaa aa 555 55 aaa 20 unlock bypass program 2x a0papd unlock bypass reset 2x 90x00 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 block erase 6 + aaa aa 555 55 aaa 80 aaa aa 555 55 ba 30 erase/ program suspend 1bka b0 erase/ program resume 1bka 30 read cfi query (2) 1 (bka) aa 98 enter extended block 3 aaa aa 555 55 aaa 88 exit extended block 4 aaa aa 555 55 aaa 90 x 00
m29dw640d 22/56 table 7. program, erase times and program, erase endurance cycles note: 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. 3. maximum value measured at worst case conditions for both temperature and v cc after 100,00 program/erase cycles. 4. maximum value measured at worst case conditions for both temperature and v cc . parameter min typ (1, 2) max (2) unit chip erase 80 400 (3) s block erase (64 kbytes) 0.8 6 (4) s erase suspend latency time 50 (4) s byte program (1, 2, 4 or 8 at-a-time) 10 200 (3) s word program (1, 2 or 4 at-a-time) 10 200 (3) s chip program (byte by byte) 80 400 (3) s chip program (word by word) 40 200 (3) s chip program (quadruple byte or double word) 20 100 (3) s chip program (octuple byte or quadruple word) 10 50 (3) s program suspend latency time 4 s program/erase cycles (per block) 100,000 cycles data retention 20 years
23/56 m29dw640d status register the m29dw640d has one status register. the status register provides information on the cur- rent or previous program or erase operations ex- ecuted in each bank. the various bits convey information and errors on the operation. bus read operations from any address within the bank, al- ways read the status register during program and erase operations. it is also read during erase sus- pend when an address within a block being erased is accessed. the bits in the status register are summarized in table 8., status register bits . data polling bit (dq7). the data polling bit can be used to identify whether the program/erase controller has successfully completed its opera- tion or if it has responded to an erase suspend. the data polling bit is output on dq7 when the status register is read. during program operations the data polling bit outputs the complement of the bit being pro- grammed to dq7. after successful completion of the program operation the memory returns to read mode and bus read operations from the ad- dress just programmed output dq7, not its com- plement. during erase operations the data polling bit out- puts ?0?, the complement of the erased state of dq7. after successful completion of the erase op- eration the memory returns to read mode. in erase suspend mode the data polling bit will output a ?1? during a bus read operation within a block being erased. the data polling bit will change from a ?0? to a ?1? when the program/erase controller has suspended the erase operation. figure 7., data polling flowchart , gives an exam- ple of how to use the data polling bit. a valid ad- dress is the address being programmed or an address within the block being erased. toggle bit (dq6). the toggle bit can be used to identify whether the program/erase controller has successfully completed its operation or if it has re- sponded to an erase suspend. the toggle bit is output on dq6 when the status register is read. during program and erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with succes- sive bus read operations at any address. after successful completion of the operation the memo- ry returns to read mode. during erase suspend mode the toggle bit will output when addressing a cell within a block being erased. the toggle bit will stop toggling when the program/erase controller has suspended the erase operation. figure 8., toggle flowchart , gives an example of how to use the data toggle bit. figures 15 and 16 describe toggle bit timing waveform. error bit (dq5). the error bit can be used to identify errors detected by the program/erase controller. the error bit is set to ?1? when a pro- gram, block erase or chip erase operation fails to write the correct data to the memory. if the error bit is set a read/reset command must be issued before other commands are issued. the error bit is output on dq5 when the status register is read. note that the program command cannot change a bit set to ?0? back to ?1? and attempting to do so will set dq5 to ?1?. a bus read operation to that ad- dress will show the bit is still ?0?. one of the erase commands must be used to set all the bits in a block or in the whole memory from ?0? to ?1?. erase timer bit (dq3). the erase timer bit can be used to identify the start of program/erase controller operation during a block erase com- mand. once the program/erase controller starts erasing the erase timer bit is set to ?1?. before the program/erase controller starts the erase timer bit is set to ?0? and additional blocks to be erased may be written to the command interface. the erase timer bit is output on dq3 when the status register is read. alternative toggle bit (dq2). the alternative toggle bit can be used to monitor the program/ erase controller during erase operations. the al- ternative toggle bit is output on dq2 when the status register is read. during chip erase and block erase operations the toggle bit changes from ?0? to ?1? to ?0?, etc., with successive bus read operations from addresses within the blocks being erased. a protected block is treated the same as a block not being erased. once the operation completes the memory returns to read mode. during erase suspend the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read operations from addresses within the blocks being erased. bus read operations to ad- dresses within blocks not being erased will output the memory cell data as if in read mode. after an erase operation that causes the error bit to be set the alternative toggle bit can be used to identify which block or blocks have caused the er- ror. the alternative toggle bit changes from ?0? to ?1? to ?0?, etc. with successive bus read opera- tions from addresses within blocks that have not erased correctly. the alternative toggle bit does not change if the addressed block has erased cor- rectly. figures 15 and 16 describe alternative toggle bit timing waveform.
m29dw640d 24/56 table 8. status register bits note: 1. unspecified data bits should be ignored. 2. figures 15 and 16 describe toggle and alternative toggle bits timing waveforms. figure 7. data polling flowchart figure 8. toggle flowchart note: ba = address of bank being programmed or erased. operation address dq7 dq6 dq5 dq3 dq2 rb program bank address dq7 to g g l e 0 ? ? 0 program during erase suspend bank address dq7 to g g l e 0 ? ? 0 program error bank address dq7 toggle 1 ? ? hi-z chip erase any address 0 toggle 0 1 toggle hi-z block erase before timeout erasing block 0 toggle 0 0 toggle 0 non-erasing block 0 toggle 0 0 no toggle 0 block erase erasing block 0 toggle 0 1 toggle hi-z non-erasing block 0 toggle 0 1 no toggle 0 erase suspend erasing block 1 no toggle 0 ? toggle hi-z non-erasing block data read as normal hi-z erase error good block address 0 toggle 1 1 no toggle 0 faulty block address 0 toggle 1 1 toggle 0 read dq5 & dq7 at valid address start read dq7 at valid address fail pass ai07760 dq7 = data yes no yes no dq5 = 1 dq7 = data yes no read dq6 address = ba start read dq6 twice address = ba fail pass ai08929b dq6 = toggle no no yes yes dq5 = 1 no yes dq6 = toggle read dq5 & dq6 address = ba
25/56 m29dw640d dual operations and multiple bank architecture the multiple bank architecture of the m29dw640d gives greater flexibility for software developers to split the code and data spaces with- in the memory array. the dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. the dual operations feature means that while pro- gramming or erasing in one bank, read operations are possible in another bank with zero latency. only one bank at a time is allowed to be in pro- gram or erase mode. however, certain commands can cross bank boundaries, which means that dur- ing an operation only the banks that are not con- cerned with the cross bank operation are available for dual operations. for example, if a block erase command is issued to erase blocks in both bank a and bank b, then only banks c or d are available for read operations while the erase is being exe- cuted. if a read operation is required in a bank, which is programming or erasing, the program or erase op- eration can be suspended. also if the suspended operation was erase then a program command can be issued to another block, so the device can have one block in erase suspend mode, one programming and other banks in read mode. by using a combination of these features, read op- erations are possible at any moment in the m29dw640d device. tables 9 and 10 show the dual operations possible in other banks and in the same bank. note that only the commonly used commands are repre- sented in these tables. table 9. dual operations allowed in other banks note: 1. if several banks are involved in a program or erase operation, then only the banks that are not concerned with the opera tion are available for dual operations. 2. only after a program or erase operation in that bank. 3. only after a program or erase suspend command in that bank. 4. only an erase resume is allowed if the bank was previously in erase suspend mode. 5. only a program resume is allowed if the bank was previously in program suspend mode. 6. read status register is not a command. the status regist er can be read during a block program or erase operation. status of bank (1) commands allowed in another bank (1) read array read status register (6) read cfi query auto select program erase program/ erase suspend program/ erase resume idle yes yes (2) yes yes yes yes yes (2) yes (3) programming yes no no no ? ? no no erasing yes no no no ? ? no no program suspended yes no yes yes no no ? yes (5) erase suspended yes no yes yes yes no ? yes (4)
m29dw640d 26/56 table 10. dual operations allowed in same bank note: 1. not allowed in the block or word that is being erased or programmed. 2. only after a program or erase operation in that bank. 3. only after a program or erase suspend command in that bank. 4. only a program suspend. 5. only an erase suspend. 6. read status register is not a command. the status regist er can be read during a block program or erase operation. 7. the status register can be read by addressing the block being erase suspended. status of bank commands allowed in same bank read array read status register (6) read cfi query auto select program erase program/ erase suspend program/ erase resume i dle ye s yes ye s ye s ye s yes yes (2) yes (3) programming no yes no no ? ? yes (4) ? erasing no yes no no ? no yes (5) ? program suspended yes (1) no ye s ye s n o ? ? ye s erase suspended yes (1) yes (7) ye s ye s yes (1) no ? yes
27/56 m29dw640d maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause per- manent damage to the device. exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. refer also to the stmicroelectronics sure program and other relevant quality docu- ments. table 11. absolute maximum ratings note: 1. compliant with the ecopack ? 7191395 specification for lead-free soldering processes. 2. not exceeding 250c for more than 30s, and peaking at 260c. 3. minimum voltage may undershoot to ?2v during trans ition and for less than 20ns during transitions. 4. maximum voltage may overshoot to v cc +2v during transition and for less than 20ns during transitions. 5. v pp must not remain at 12v for more than a total of 80hrs. symbol parameter min max unit t bias temperature under bias ?50 125 c t stg storage temperature ?65 150 c t lead lead temperature during soldering (1) 260 (2) c v io input or output voltage (3,4) ?0.6 v cc +0.6 v v cc supply voltage ?0.6 4 v v id identification voltage ?0.6 13.5 v v pp (5) program voltage ?0.6 13.5 v
m29dw640d 28/56 dc and ac parameters this section summarizes the operating measure- ment conditions, and the dc and ac characteris- tics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 12., operating and ac measurement conditions . designers should check that the operating conditions in their circuit match the operating conditions when rely- ing on the quoted parameters. table 12. operating and ac measurement conditions figure 9. ac measurement i/o waveform figure 10. ac measurement load circuit table 13. device capacitance note: sampled only, not 100% tested. parameter m29dw640d unit 70 90 min max min max v cc supply voltage 2.7 3.6 2.7 3.6 v ambient operating temperature ?40 85 ?40 85 c load capacitance (c l ) 30 30 pf input rise and fall times 10 10 ns input pulse voltages 0 to v cc 0 to v cc v input and output timing ref. voltages v cc /2 v cc /2 v ai05557 v cc 0v v cc /2 ai05558 c l c l includes jig capacitance device under test 25k ? v cc 25k ? v cc 0.1f v pp 0.1f symbol parameter test condition min max unit c in input capacitance v in = 0v 6pf c out output capacitance v out = 0v 12 pf
29/56 m29dw640d table 14. dc characteristics note: 1. sampled only, not 100% tested. 2. in dual operations the supply current will be the sum of i cc1 (read) and i cc3 (program/erase). symbol parameter test condition min max unit i li input leakage current 0v v in v cc 1 a i lo output leakage current 0v v out v cc 1 a i cc1 (2) supply current (read) e = v il , g = v ih , f = 6mhz 10 ma i cc2 supply current (standby) e = v cc 0.2v, rp = v cc 0.2v 100 a i cc3 (1,2) supply current (program/ erase) program/erase controller active v pp /wp = v il or v ih 20 ma v pp /wp = v pp 20 ma v il input low voltage ?0.5 0.8 v v ih input high voltage 0.7v cc v cc +0.3 v v pp voltage for v pp /wp program acceleration v cc = 2.7v 10% 11.5 12.5 v i pp current for v pp /wp program acceleration v cc =2.7v 10% 15 ma v ol output low voltage i ol = 1.8ma 0.45 v v oh output high voltage i oh = ?100 a v cc ?0.4 v v id identification voltage 11.5 12.5 v v lko program/erase lockout supply voltage 1.8 2.3 v
m29dw640d 30/56 figure 11. random read ac waveforms figure 12. page read ac waveforms ai05559 tavav tavqv taxqx telqx tehqz tglqv tglqx tghqx valid a0-a21/ a?1 g dq0-dq7/ dq8-dq15 e telqv tehqx tghqz valid tbhqv telbl/telbh tblqz byte ai07762 tehqz tghqx valid a2-a21/ a?1 g dq0-dq7/ dq8-dq15 e telqv tehqx tghqz valid tbhqv telbl/telbh tblqz byte a0-a1 valid valid valid valid valid valid valid tglqv tavqv tavqv1
31/56 m29dw640d table 15. read ac characteristics note: 1. sampled only, not 100% tested. symbol alt parameter test condition m29dw640d unit 70 90 t avav t rc address valid to next address valid e = v il , g = v il min 70 90 ns t avqv t acc address valid to output valid e = v il , g = v il max 70 90 ns t avqv1 t page address valid to output valid (page) e = v il , g = v il max 25 30 ns t elqx (1) t lz chip enable low to output transition g = v il min 0 0 ns t elqv t ce chip enable low to output valid g = v il max 70 90 ns t glqx (1) t olz output enable low to output transition e = v il min 0 0 ns t glqv t oe output enable low to output valid e = v il max 30 35 ns t ehqz (1) t hz chip enable high to output hi-z g = v il max 25 30 ns t ghqz (1) t df output enable high to output hi-z e = v il max 25 30 ns t ehqx t ghqx t axqx t oh chip enable, output enable or address transition to output transition min 0 0 ns t elbl t elbh t elfl t elfh chip enable to byte low or high max 5 5 ns t blqz t flqz byte low to output hi-z max 25 30 ns t bhqv t fhqv byte high to output valid max 30 40 ns
m29dw640d 32/56 figure 13. write ac waveforms, write enable controlled table 16. write ac characteristics, write enable controlled note: 1. sampled only, not 100% tested. symbol alt parameter m29dw640d unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t elwl t cs chip enable low to write enable low min 0 0 ns t wlwh t wp write enable low to write enable high min 45 50 ns t dvwh t ds input valid to write enable high min 45 50 ns t whdx t dh write enable high to input transition min 0 0 ns t wheh t ch write enable high to chip enable high min 0 0 ns t whwl t wph write enable high to write enable low min 30 30 ns t avwl t as address valid to write enable low min 0 0 ns t wlax t ah write enable low to address transition min 45 50 ns t ghwl output enable high to write enable low min 0 0 ns t whgl t oeh write enable high to output enable low min 0 0 ns t whrl (1) t busy program/erase valid to rb low max 30 35 ns t vchel t vcs v cc high to chip enable low min 50 50 s ai05560 e g w a0-a21/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchel twheh twhwl telwl tavwl twhgl twlax twhdx tavav tdvwh twlwh tghwl rb twhrl
33/56 m29dw640d figure 14. write ac waveforms, chip enable controlled table 17. write ac characteristics, chip enable controlled note: 1. sampled only, not 100% tested. symbol alt parameter m29dw640d unit 70 90 t avav t wc address valid to next address valid min 70 90 ns t wlel t ws write enable low to chip enable low min 0 0 ns t eleh t cp chip enable low to chip enable high min 45 50 ns t dveh t ds input valid to chip enable high min 45 50 ns t ehdx t dh chip enable high to input transition min 0 0 ns t ehwh t wh chip enable high to write enable high min 0 0 ns t ehel t cph chip enable high to chip enable low min 30 30 ns t avel t as address valid to chip enable low min 0 0 ns t elax t ah chip enable low to address transition min 45 50 ns t ghel output enable high chip enable low min 0 0 ns t ehgl t oeh chip enable high to output enable low min 0 0 ns t ehrl (1) t busy program/erase valid to rb low max 30 35 ns t vchwl t vcs v cc high to write enable low min 50 50 s ai05561 e g w a0-a21/ a?1 dq0-dq7/ dq8-dq15 valid valid v cc tvchwl tehwh tehel twlel tavel tehgl telax tehdx tavav tdveh teleh tghel rb tehrl
m29dw640d 34/56 figure 15. toggle and alternative toggle bits mechanism, chip enable controlled note: 1. the toggle bit is output on dq6. 2. the alternative toggle bit is output on dq2. figure 16. toggle and alternative toggle bits mechanism, output enable controlled note: 1. the toggle bit is output on dq6. 2. the alternative toggle bit is output on dq2. table 18. toggle and alternative toggle bits ac characteristics note: t elqv and t glqv values are presented in table 15., read ac characteristics . symbol alt parameter m29dw640d unit 70 90 t axel address transition to chip enable low min 10 10 ns t axgl address transition to output enable low min 10 10 ns ai08914c g a0-a20 dq2 (1) /dq6 (2) e taxel telqv data data toggle/ alternative toggle bit telqv address in the bank being programmed or erased read operation outside the bank being programmed or erased address outside the bank being programmed or erased address outside the bank being programmed or erased toggle/ alternative toggle bit read operation outside the bank being programmed or erased read operation in the bank being programmed or erased ai08915c g a0-a20 dq2 (1) /dq6 (2) e taxgl tglqv data data toggle/ alternative toggle bit tglqv address in the bank being programmed or erased read operation outside the bank being programmed or erased address outside the bank being programmed or erased address outside the bank being programmed or erased toggle/ alternative toggle bit read operation outside the bank being programmed or erased read operation in the bank being programmed or erased
35/56 m29dw640d figure 17. reset/block temporary unprotect ac waveforms table 19. reset/block temporary unprotect ac characteristics note: 1. sampled only, not 100% tested. figure 18. accelerated program timing waveforms symbol alt parameter m29dw640d unit 70 90 t phwl (1) t phel t phgl (1) t rh rp high to write enable low, chip enable low, output enable low min 50 50 ns t rhwl (1) t rhel (1) t rhgl (1) t rb rb high to write enable low, chip enable low, output enable low min 0 0 ns t plpx t rp rp pulse width min 500 500 ns t plyh t ready rp low to read mode max 50 50 s t phphh (1) t vidr rp rise time to v id min 500 500 ns t vhvpp (1) v pp rise and fall time min 250 250 ns ai02931b rb w, rp tplpx tphwl, tphel, tphgl tplyh tphphh e, g trhwl, trhel, trhgl ai05563 v pp /wp v pp v il or v ih tvhvpp tvhvpp
m29dw640d 36/56 package mechanical figure 19. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package outline note: drawing is not to scale. table 20. tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.080 0.0031 d1 12.000 11.900 12.100 0.4724 0.4685 0.4764 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? ? l 0.600 0.500 0.700 0.0236 0.0197 0.0276 l1 0.800 0.0315 305305 tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp
37/56 m29dw640d figure 20. tfbga63 7x11mm - 6x8 active ball array, 0.8mm pitch, package outline note: drawing is not to scale. table 21. tfbga63 7x11mm - 6x8 active ball array, 0.8mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.250 0.0098 a2 0.900 0.0354 b 0.350 0.450 0.0138 0.0177 d 7.000 6.900 7.100 0.2756 0.2717 0.2795 d1 5.600 ? ? 0.2205 ? ? ddd ? ? 0.100 ? ? 0.0039 e 11.000 10.900 11.100 0.4331 0.4291 0.4370 e1 8.800 ? ? 0.3465 ? ? e 0.800 ? ? 0.0315 ? ? fd 0.700 ? ? 0.0276 ? ? fe 1.100 ? ? 0.0433 ? ? sd 0.400 ? ? 0.0157 ? ? se 0.400 ? ? 0.0157 ? ? e d eb sd se a2 a1 a bga-z33 ddd fd d1 e1 e fe ball "a1"
m29dw640d 38/56 part numbering table 22. ordering information scheme note: this product is also available with the extended block factory locked. for further details and ordering information contact your nearest st sales office. devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. example: m29dw640d 70 n 1 t device type m29 architecture d = dual or multiple bank operating voltage w = v cc = 2.7 to 3.6v device function 640d = 64 mbit (x8/x16), boot block, 8+24+24+8 partitioning speed 70 = 70ns 90 = 90ns package n = tsop48: 12 x 20 mm za = fbga63: 7 x 11mm, 0.80 mm pitch temperature range 1 = 0 to 70 c 6 = ?40 to 85 c option blank = standard packing t = tape & reel packing e = lead-free package, standard packing f = lead-free package, tape & reel packing
39/56 m29dw640d appendix a. block addresses table 23. block addresses bank block (kbytes/ kwords) protection block group (x8) (x16) bank a 0 8/4 protection group 000000h-001fffh (1) 000000h?000fffh (1) 1 8/4 protection group 002000h-003fffh (1) 001000h?001fffh (1) 2 8/4 protection group 004000h-005fffh (1) 002000h?002fffh (1) 3 8/4 protection group 006000h-007fffh (1) 003000h?003fffh (1) 4 8/4 protection group 008000h-009fffh (1) 004000h?004fffh (1) 5 8/4 protection group 00a000h-00bfffh (1) 005000h?005fffh (1) 6 8/4 protection group 00c000h-00dfffh (1) 006000h?006fffh (1) 7 8/4 protection group 00e000h-00ffffh (1) 007000h?007fffh (1) 8 64/32 protection group 010000h-01ffffh 008000h?00ffffh 9 64/32 020000h-02ffffh 010000h?017fffh 10 64/32 030000h-03ffffh 018000h?01ffffh 11 64/32 protection group 040000h-04ffffh 020000h?027fffh 12 64/32 050000h-05ffffh 028000h?02ffffh 13 64/32 060000h-06ffffh 030000h?037fffh 14 64/32 070000h-07ffffh 038000h?03ffffh 15 64/32 protection group 080000h-08ffffh 040000h?047fffh 16 64/32 090000h-09ffffh 048000h?04ffffh 17 64/32 0a0000h-0affffh 050000h?057fffh 18 64/32 0b0000h-0bffffh 058000h?05ffffh 19 64/32 protection group 0c0000h-0cffffh 060000h?067fffh 20 64/32 0d0000h-0dffffh 068000h?06ffffh 21 64/32 0e0000h-0effffh 070000h?077fffh 22 64/32 0f0000h-0fffffh 078000h?07ffffh
m29dw640d 40/56 bank b 23 64/32 protection group 100000h-10ffffh 080000h?087fffh 24 64/32 110000h-11ffffh 088000h?08ffffh 25 64/32 120000h-12ffffh 090000h?097fffh 26 64/32 130000h-13ffffh 098000h?09ffffh 27 64/32 protection group 140000h-14ffffh 0a0000h?0a7fffh 28 64/32 150000h-15ffffh 0a8000h?0affffh 29 64/32 160000h-16ffffh 0b0000h?0b7fffh 30 64/32 170000h-17ffffh 0b8000h?0bffffh 31 64/32 protection group 180000h-18ffffh 0c0000h?0c7fffh 32 64/32 190000h-19ffffh 0c8000h?0cffffh 33 64/32 1a0000h-1affffh 0d0000h?0d7fffh 34 64/32 1b0000h-1bffffh 0d8000h?0dffffh 35 64/32 protection group 1c0000h-1cffffh 0e0000h?0e7fffh 36 64/32 1d0000h-1dffffh 0e8000h?0effffh 37 64/32 1e0000h-1effffh 0f0000h?0f7fffh 38 64/32 1f0000h-1fffffh 0f8000h?0fffffh 39 64/32 protection group 200000h-20ffffh 100000h?107fffh 40 64/32 210000h-21ffffh 108000h?10ffffh 41 64/32 220000h-22ffffh 110000h?117fffh 42 64/32 230000h-23ffffh 118000h?11ffffh 43 64/32 protection group 240000h-24ffffh 120000h?127fffh 44 64/32 250000h-25ffffh 128000h?12ffffh 45 64/32 260000h-26ffffh 130000h?137fffh 46 64/32 270000h-27ffffh 138000h?13ffffh 47 64/32 protection group 280000h-28ffffh 140000h?147fffh 48 64/32 290000h-29ffffh 148000h?14ffffh 49 64/32 2a0000h-2affffh 150000h?157fffh 50 64/32 2b0000h-2bffffh 158000h?15ffffh 51 64/32 protection group 2c0000h-2cffffh 160000h?167fffh 52 64/32 2d0000h-2dffffh 168000h?16ffffh 53 64/32 2e0000h-2effffh 170000h?177fffh 54 64/32 2f0000h-2fffffh 178000h?17ffffh bank block (kbytes/ kwords) protection block group (x8) (x16)
41/56 m29dw640d bank b 55 64/32 protection group 300000h-30ffffh 180000h?187fffh 56 64/32 310000h-31ffffh 188000h?18ffffh 57 64/32 320000h-32ffffh 190000h?197fffh 58 64/32 330000h-33ffffh 198000h?19ffffh 59 64/32 protection group 340000h-34ffffh 1a0000h?1a7fffh 60 64/32 350000h-35ffffh 1a8000h?1affffh 61 64/32 360000h-36ffffh 1b0000h?1b7fffh 62 64/32 370000h-37ffffh 1b8000h?1bffffh 63 64/32 protection group 380000h-38ffffh 1c0000h?1c7fffh 64 64/32 390000h-39ffffh 1c8000h?1cffffh 65 64/32 3a0000h-3affffh 1d0000h?1d7fffh 66 64/32 3b0000h-3bffffh 1d8000h?1dffffh 67 64/32 protection group 3c0000h-3cffffh 1e0000h?1e7fffh 68 64/32 3d0000h-3dffffh 1e8000h?1effffh 69 64/32 3e0000h-3effffh 1f0000h?1f7fffh 70 64/32 3f0000h-3fffffh 1f8000h?1fffffh bank c 71 64/32 protection group 400000h?40ffffh 200000h?207fffh 72 64/32 410000h?41ffffh 208000h?20ffffh 73 64/32 420000h?42ffffh 210000h?217fffh 74 64/32 430000h?43ffffh 218000h?21ffffh 75 64/32 protection group 440000h?44ffffh 220000h?227fffh 76 64/32 450000h?45ffffh 228000h?22ffffh 77 64/32 460000h?46ffffh 230000h?237fffh 78 64/32 470000h?47ffffh 238000h?23ffffh 79 64/32 protection group 480000h?48ffffh 240000h?247fffh 80 64/32 490000h?49ffffh 248000h?24ffffh 81 64/32 4a0000h?4affffh 250000h?257fffh 82 64/32 4b0000h?4bffffh 258000h?25ffffh 83 64/32 protection group 4c0000h?4cffffh 260000h?267fffh 84 64/32 4d0000h?4dffffh 268000h?26ffffh 85 64/32 4e0000h?4effffh 270000h?277fffh 86 64/32 4f0000h?4fffffh 278000h?27ffffh bank block (kbytes/ kwords) protection block group (x8) (x16)
m29dw640d 42/56 bank c 87 64/32 protection group 500000h?50ffffh 280000h?287fffh 88 64/32 510000h?51ffffh 288000h?28ffffh 89 64/32 520000h?52ffffh 290000h?297fffh 90 64/32 530000h?53ffffh 298000h?29ffffh 91 64/32 protection group 540000h?54ffffh 2a0000h?2a7fffh 92 64/32 550000h?55ffffh 2a8000h?2affffh 93 64/32 560000h?56ffffh 2b0000h?2b7fffh 94 64/32 570000h?57ffffh 2b8000h?2bffffh 95 64/32 protection group 580000h?58ffffh 2c0000h?2c7fffh 96 64/32 590000h?59ffffh 2c8000h?2cffffh 97 64/32 5a0000h?5affffh 2d0000h?2d7fffh 98 64/32 5b0000h?5bffffh 2d8000h?2dffffh 99 64/32 protection group 5c0000h?5cffffh 2e0000h?2e7fffh 100 64/32 5d0000h?5dffffh 2e8000h?2effffh 101 64/32 5e0000h?5effffh 2f0000h?2f7fffh 102 64/32 5f0000h?5fffffh 2f8000h?2fffffh 103 64/32 protection group 600000h?60ffffh 300000h?307fffh 104 64/32 610000h?61ffffh 308000h?30ffffh 105 64/32 620000h?62ffffh 310000h?317fffh 106 64/32 630000h?63ffffh 318000h?31ffffh 107 64/32 protection group 640000h?64ffffh 320000h?327fffh 108 64/32 650000h?65ffffh 328000h?32ffffh 109 64/32 660000h?66ffffh 330000h?337fffh 110 64/32 670000h?67ffffh 338000h?33ffffh 111 64/32 protection group 680000h?68ffffh 340000h?347fffh 112 64/32 690000h?69ffffh 348000h?34ffffh 113 64/32 6a0000h?6affffh 350000h?357fffh 114 64/32 6b0000h?6bffffh 358000h?35ffffh 115 64/32 protection group 6c0000h?6cffffh 360000h?367fffh 116 64/32 6d0000h?6dffffh 368000h?36ffffh 117 64/32 6e0000h?6effffh 370000h?377fffh 118 64/32 6f0000h?6fffffh 378000h?37ffffh bank block (kbytes/ kwords) protection block group (x8) (x16)
43/56 m29dw640d bank d 119 64/32 protection group 700000h?70ffffh 380000h?387fffh 120 64/32 710000h?71ffffh 388000h?38ffffh 121 64/32 720000h?72ffffh 390000h?397fffh 122 64/32 730000h?73ffffh 398000h?39ffffh 123 64/32 protection group 740000h?74ffffh 3a0000h?3a7fffh 124 64/32 750000h?75ffffh 3a8000h?3affffh 125 64/32 760000h?76ffffh 3b0000h?3b7fffh 126 64/32 770000h?77ffffh 3b8000h?3bffffh 127 64/32 protection group 780000h?78ffffh 3c0000h?3c7fffh 128 64/32 790000h?79ffffh 3c8000h?3cffffh 129 64/32 7a0000h?7affffh 3d0000h?3d7fffh 130 64/32 7b0000h?7bffffh 3d8000h?3dffffh 131 64/32 protection group 7c0000h?7cffffh 3e0000h?3e7fffh 132 64/32 7d0000h?7dffffh 3e8000h?3effffh 133 64/32 7e0000h?7effffh 3f0000h?3f7fffh 134 8/4 protection group 7f0000h?7f1fffh 3f8000h?3f8fffh 135 8/4 protection group 7f2000h?7f3fffh 3f9000h?3f9fffh 136 8/4 protection group 7f4000h?7f5fffh 3fa000h?3fafffh 137 8/4 protection group 7f6000h?7f7fffh 3fb000h?3fbfffh 138 8/4 protection group 7f8000h?7f9fffh 3fc000h?3fcfffh 139 8/4 protection group 7fa000h?7fbfffh 3fd000h?3fdfffh 140 8/4 protection group 7fc000h?7fdfffh 3fe000h?3fefffh 141 8/4 protection group 7fe000h?7fffffh 3ff000h?3fffffh bank block (kbytes/ kwords) protection block group (x8) (x16)
m29dw640d 44/56 appendix b. common flash interface (cfi) the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the read cfi query command is issued the addressed bank enters read cfi query mode and read operations in the same bank (a21-a19) out- put the cfi data. tables 24 , 25 , 26 , 27 , 28 and 29 show the addresses (a-1, a0-a10) used to retrieve the data. the cfi data structure also contains a security area where a 64 bit unique security number is writ- ten (see table 29., security code area ). this area can be accessed only in read mode by the final user. it is impossible to change the security num- ber after it has been written by st. table 24. query structure overview note: query data are always presented on the lowest order data outputs. table 25. cfi query identification string note: query data are always presented on the lowest order data outputs (dq7-dq0) only. dq8-dq15 are ?0?. address sub-section name description x16 x8 10h 20h cfi query identification string command set id and algorithm data offset 1bh 36h system interface information device timing & voltage information 27h 4eh device geometry definition flash device layout 40h 80h primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) 61h c2h security code area 64 bit unique device number address data description value x16 x8 10h 20h 0051h ?q? 11h 22h 0052h query unique ascii string "qry" "r" 12h 24h 0059h "y" 13h 26h 0002h primary algorithm command set and control interface id code 16 bit id code defining a specific algorithm amd compatible 14h 28h 0000h 15h 2ah 0040h address for primary algorithm extended query table (see table 28 )p = 40h 16h 2ch 0000h 17h 2eh 0000h alternate vendor command set and control interface id code second vendor - specified algorithm supported na 18h 30h 0000h 19h 32h 0000h address for alternate algorithm extended query table na 1ah 34h 0000h
45/56 m29dw640d table 26. cfi query system interface information table 27. device geometry definition address data description value x16 x8 1bh 36h 0027h v cc logic supply minimum program/erase voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 mv 2.7v 1ch 38h 0036h v cc logic supply maximum program/erase voltage bit 7 to 4bcd value in volts bit 3 to 0bcd value in 100 mv 3.6v 1dh 3ah 00b5h v pp [programming] supply minimum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 11.5v 1eh 3ch 00c5h v pp [programming] supply maximum program/erase voltage bit 7 to 4hex value in volts bit 3 to 0bcd value in 100 mv 12.5v 1fh 3eh 0004h typical timeout per single byte/word program = 2 n s 16s 20h 40h 0000h typical timeout for minimum size write buffer program = 2 n s na 21h 42h 000ah typical timeout per individual block erase = 2 n ms 1s 22h 44h 0000h typical timeout for full chip erase = 2 n ms na 23h 46h 0004h maximum timeout for byte/word program = 2 n times typical 256 s 24h 48h 0000h maximum timeout for write buffer program = 2 n times typical na 25h 4ah 0003h maximum timeout per individual block erase = 2 n times typical 8s 26h 4ch 0000h maximum timeout for chip erase = 2 n times typical na address data description value x16 x8 27h 4eh 0017h device size = 2 n in number of bytes 8 mbytes 28h 29h 50h 52h 0002h 0000h flash device interface code description x8, x16 async. 2ah 2bh 54h 56h 0003h 0000h maximum number of bytes in multi-byte program or page = 2 n 8 2ch 58h 0003h number of erase block regions (1) . it specifies the number of regions containing contiguous erase blocks of the same size. 3 2dh 2eh 5ah 5ch 0007h 0000h erase block region 1 information number of erase blocks of identical size = 0007h+1 8 2fh 30h 5eh 60h 0020h 0000h erase block region 1 information block size in region 1 = 0020h * 256 byte 8 kbytes 31h 32h 62h 64h 007dh 0000h erase block region 2 information number of erase blocks of identical size = 007dh+1 126 33h 34h 66h 68h 0000h 0001h erase block region 2 information block size in region 2 = 0100h * 256 byte 64 kbytes
m29dw640d 46/56 note: 1. erase block region 1 corresponds to addresses 000000h to 007fffh; erase block region 2 corresponds to addresses 008000h to 3f7fffh and erase block region 3 co rresponds to addresse s 3f8000h to 3fffffh. table 28. primary algorithm-specific extended query table 35h 36h 6ah 6ch 0007h 0000h erase block region 3 information number of erase blocks of identical size = 0007h + 1 8 37h 38h 6eh 70h 0020h 0000h erase block region 3 information block size in region 3 = 0020h * 256 bytes 8 kbytes 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information address data description value x16 x8 40h 80h 0050h primary algorithm extended query table unique ascii string ?pri? "p" 41h 82h 0052h "r" 42h 84h 0049h "i" 43h 86h 0031h major version number, ascii "1" 44h 88h 0033h minor version number, ascii "3" 45h 8ah 0000h address sensitive unlock (bits 1 to 0) 00 = required, 01= not required silicon revision number (bits 7 to 2) yes 46h 8ch 0002h erase suspend 00 = not supported, 01 = read only, 02 = read and write 2 47h 8eh 0001h block protection 00 = not supported, x = number of sectors in per group 1 48h 90h 0001h temporary block unprotect 00 = not supported, 01 = supported yes 49h 92h 0005h block protect /unprotect 04 = m29w400b 05 = m29dw640d 5 4ah 94h 0077h simultaneous operations, x = number of blocks (excluding bank a) 119 4bh 96h 0000h burst mode, 00 = not supported, 01 = supported no 4ch 98h 0001h page mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word yes 4dh 9ah 00b5h v pp supply minimum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 11.5v 4eh 9ch 00c5h v pp supply maximum program/erase voltage bit 7 to 4 hex value in volts bit 3 to 0 bcd value in 100 mv 12.5v address data description value x16 x8
47/56 m29dw640d table 29. security code area 4fh 9eh 0001h top/bottom boot block flag 00h = uniform device 01h = 8 x8 kbyte blocks, top and bottom boot with write protect 02h = bottom boot device 03h = top boot device 04h = both top and bottom t/b 50h a0h 0001h program suspend, 00 = not supported, 01 = supported yes 57h aeh 0004h bank organization, 00 = data at 4ah is zero x = number of banks 4 58h b0h 0017h bank a information x = number of blocks in bank a 23 59h b2h 0030h bank b information x = number of blocks in bank b 48 5ah b4h 0030h bank c information x = number of blocks in bank c 48 5bh b6h 0017h bank d information x = number of blocks in bank d 23 address data description x16 x8 61h c3h, c2h xxxx 64 bit: unique device number 62h c5h, c4h xxxx 63h c7h, c6h xxxx 64h c9h, c8h xxxx address data description value x16 x8
m29dw640d 48/56 appendix c. extended memory block the m29dw640d has an extra block, the extend- ed block, that can be accessed using a dedicated command. this extended block is 128 words in x16 mode and 256 bytes in x8 mode. it is used as a security block (to provide a permanent security identifica- tion number) or to store additional information. the extended block is either factory locked or customer lockable, its status is indicated by bit dq7. this bit is permanently set to either ?1? or ?0? at the factory and cannot be changed. when set to ?1?, it indicates that the device is factory locked and the extended block is protected. when set to ?0?, it indicates that the device is customer lockable and the extended block is unprotected. bit dq7 being permanently locked to either ?1? or ?0? is another security feature which ensures that a customer lockable device cannot be used instead of a facto- ry locked one. bit dq7 is the most significant bit in the extended block verify code and a specific procedure must be followed to read it. see ?extended block indica- tor bit? in tables 3 and 4 , bus operations, byte = v il and bus operations, byte = v ih , respectively, for details of how to read bit dq7. the extended block can only be accessed when the device is in extended block mode. for details of how the extended block mode is entered and exited, refer to the enter extended block com- mand and exit extended block command para- graphs, and to tables 5 and 6 , ? commands, 16-bit mode, byte = v ih ? and ? commands, 8-bit mode, byte = v il ?, respectively. factory locked extended block in devices where the extended block is factory locked, the security identification number is writ- ten to the extended block address space (see ta- ble 30., extended block address and data ) in the factory. the dq7 bit is set to ?1? and the extended block cannot be unprotected. customer lockable extended block a device where the extended block is customer lockable is delivered with the dq7 bit set to ?0? and the extended block unprotected. it is up to the customer to program and protect the extended block but care must be taken because the protec- tion of the extended block is not reversible. there are two ways of protecting the extended block: issue the enter extended block command to place the device in extended block mode, then use the in-system technique with rp either at v ih or at v id (refer to appendix d , in- system technique and to the corresponding flowcharts, figures 23 and 24 , for a detailed explanation of the technique). issue the enter extended block command to place the device in extended block mode, then use the programmer technique (refer to appendix d , programmer technique and to the corresponding flowcharts, figures 21 and 22 , for a detailed explanation of the technique). once the extended block is programmed and pro- tected, the exit extended block command must be issued to exit the extended block mode and return the device to read mode. table 30. extended block address and data note: 1. see table 23., block addresses . 2. ens = electronic serial number. device address (1) data x8 x16 factory locked customer lockable m29dw640d 000000h-00000fh 000000h-000007h random number security identification number determined by customer 000010h-000020h 000008h-00000fh esn (2) 000021h-0000ffh 000010h-00007fh unavailable
49/56 m29dw640d appendix d. block protection block protection can be used to prevent any oper- ation from modifying the data stored in the memo- ry. the blocks are protected in groups, refer to appendix a , table 23 for details of the protection groups. once protected, program and erase op- erations within the protected group fail to change the data. there are three techniques that can be used to control block protection, these are the program- mer technique, the in-system technique and tem- porary unprotection. temporary unprotection is controlled by the reset/block temporary unpro- tection pin, rp ; this is described in the signal de- scriptions section. to protect the extended block issue the enter ex- tended block command and then use either the programmer or in-system technique. once pro- tected issue the exit extended block command to return to read mode. the extended block protec- tion is irreversible, once protected the protection cannot be undone. programmer technique the programmer technique uses high (v id ) volt- age levels on some of the bus pins. these cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in programming equipment. to protect a group of blocks follow the flowchart in figure 21., programmer equipment group protect flowchart . to unprotect the whole chip it is neces- sary to protect all of the groups first, then all groups can be unprotected at the same time. to unprotect the chip follow figure 22., programmer equipment chip unprotect flowchart . table 31., programmer technique bus operations, byte = v ih or v il , gives a summary of each oper- ation. the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not abort the procedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. in-system technique the in-system technique requires a high voltage level on the reset/blocks temporary unprotect pin, rp (1) . this can be achieved without violating the maximum ratings of the components on the mi- croprocessor bus, therefore this technique is suit- able for use after the memory has been fitted to the system. to protect a group of blocks follow the flowchart in figure 23., in-system equipment group protect flowchart . to unprotect the whole chip it is neces- sary to protect all of the groups first, then all the groups can be unprotected at the same time. to unprotect the chip follow figure 24., in-system equipment chip unprotect flowchart . the timing on these flowcharts is critical. care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. do not allow the microprocessor to service interrupts that will upset the timing and do not abort the pro- cedure before reaching the end. chip unprotect can take several seconds and a user message should be provided to show that the operation is progressing. note: 1. rp can be either at v ih or at v id when using the in-sys- tem technique to protect the extended block. table 31. programmer technique bus operations, byte = v ih or v il note: 1. block protection groups are shown in appendix d , table 23 . operation e g w address inputs a0-a21 data inputs/outputs dq15a?1, dq14-dq0 block (group) protect (1) v il v id v il pulse a9 = v id , a12-a21 block address others = x x chip unprotect v id v id v il pulse a9 = v id , a12 = v ih , a15 = v ih others = x x block (group) protect verify v il v il v ih a0 = v il , a1 = v ih , a2 = v il , a3 = v il , a6 = v il , a9 = v id , a12-a21 block address others = x pass = xx01h retry = xx00h. block (group) unprotect verify v il v il v ih a0 = v il , a1 = v ih , a2 = v il , a3 = v il , a6 = v ih , a9 = v id , a12-a21 block address others = x pass = xx00h retry = xx01h.
m29dw640d 50/56 figure 21. programmer equipment group protect flowchart note: 1. block protection groups are shown in appendix d , table 23 . address = group address ai07756 g, a9 = v id , e = v il n = 0 wait 4s wait 100s w = v il w = v ih e, g = v ih , a1 = v ih a0, a2, a3, a6 = v il a9 = v ih e, g = v ih ++n = 25 start fail pass yes no data = 01h yes no w = v ih e = v il wait 4s g = v il wait 60ns read data verify protect set-up end a9 = v ih e, g = v ih
51/56 m29dw640d figure 22. programmer equipment chip unprotect flowchart note: 1. block protection groups are shown in appendix d , table 23 . protect all groups ai07757 a6, a12, a15 = v ih (1) e, g, a9 = v id data = 00h w = v ih e, g = v ih address = current group address a0, a2, a3 = v il a1, a6 = v ih wait 10ms increment current group n = 0 current group = 0 wait 4s w = v il ++n = 1000 start yes yes no no last group yes no e = v il wait 4s g = v il wait 60ns read data fail pass verify unprotect set-up end a9 = v ih e, g = v ih a9 = v ih e, g = v ih
m29dw640d 52/56 figure 23. in-system equipment group protect flowchart note: 1. block protection groups are shown in appendix d , table 23 . 2. rp can be either at v ih or at v id when using the in-system technique to protect the extended block. ai07758 write 60h address = group address a0, a2, a3, a6 = v il, a1 = v ih n = 0 wait 100s write 40h address = group address a0, a2, a3, a6 = v il, a1 = v ih rp = v ih ++n = 25 start pass yes no data = 01h yes no rp = v ih wait 4s verify protect set-up end read data address = group address a0, a2, a3, a6 = v il, a1 = v ih rp = v id issue read/reset command write 60h address = group address a0, a2, a3, a6 = v il, a1 = v ih issue read/reset command fail
53/56 m29dw640d figure 24. in-system equipment chip unprotect flowchart note: 1. block protection groups are shown in appendix d , table 23 . ai07759 write 60h any address with a0, a2, a3 = v il, a1, a6 = v ih n = 0 current group = 0 wait 10ms write 40h address = current group address a0, a2, a3 = v il, a1, a6 = v ih rp = v ih ++n = 1000 start fail pass no data = 00h yes no rp = v ih wait 4s read data address = current group address a0, a2, a3 = v il, a1, a6 = v ih rp = v id issue read/reset command issue read/reset command protect all groups increment current group last group yes no write 60h any address with a0, a2, a3, a6 = v il, a1 = v ih verify unprotect set-up end yes
m29dw640d 54/56 revision history table 32. document revision history date version revision details 10-dec-2002 1.0 document written 27-feb-2003 1.1 typical after 100k w/e cycles column removed from table 7., program, erase times and program, erase endurance cycles , and data retention and erase suspend latency time parameters added. device code corrected. address on dq7-dq0 modified for the cycle no.2 of the read device code in table 3., bus operations, byte = v il . lead-free package options e and f added to table 22., ordering information scheme . 01-apr-2003 1.2 document status promoted to preliminary data. page mode added, appendix c ?extended memory block? added. v ss signal description clarified. parameter i id removed from dc characteristics table. read cfi query command address clarified. program suspend latency time added to table 7., program, erase times and program, erase endurance cycles . dual operations section added. 15-may-2003 1.3 note added to table 22., ordering information scheme . table 20., tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package mechanical data and figure 19., tsop48 ? 48 lead plastic thin small outline, 12 x 20mm, package outline , modified. data modified at addresses 4ah and 4fh in table 28 , primary algorithm-specific extended query table and at address 2ch in table 27 , device geometry definition . 18-jul-2003 2.0 note 1 removed from: figures 5 and 6 , block address (x8 and x16, respectively), and from table 23 , block addresses . rb bit is high-z (instead of 1), in table 8 . auto select command description modified. extended memory block size modified in appendix c . 15-sep-2003 2.1 figures 15 and 16 , toggle and alternative toggle bits mechanisms added. table 16, toggle and alternative toggle bits ac characteristics added. address 38h modified, addresses 39h to 3ch added in device geometry definition . address 44h modified in table 28., primary algorithm-specific extended query table . 07-oct-2003 2.2 figures 15 and 16 , toggle and alternative toggle bits mechanisms modified; and notes 1 and 2 added. table 18., toggle and alternative toggle bits ac characteristics updated. figure 8., toggle flowchart renamed and modified, note added. 07-nov-2003 2.3 bank address modified in the auto select command, read cfi query command and common flash interface (cfi) sections. addresses for read cfi query command modified in the read cfi command section. 18-nov-2003 2.4 vcc minimum value updated in table 12., operating and ac measurement conditions . v pp and i pp test conditions updated in table 14., dc characteristics . customer lockable extended block mechanism modified in appendix c., extended memory block . appendix d., block protection updated: note 1 added in the in-system technique section and note 2 added below figure 23., in-system equipment group protect flowchart . 19-dec-2003 2.5 architecture identifier updated in table 22, part numbering scheme. customer lockable extended block mechanism modified in appendix c., extended memory block . appendix d., block protection updated: note 1 updated in the in-system technique section and note 2 updated below figure 23., in-system equipment group protect flowchart . 12-aug-2004 3.0 figure 2., logic diagram and figure 3., tsop connections updated. table 9., dual operations allowed in other banks and table 10., dual operations allowed in same bank updated in dual operations and multiple bank architecture section.
55/56 m29dw640d 10-dec-2004 4.0 status of ready/busy signal for program error, chip erase and block erase modified in table 8., status register bits . date version revision details
m29dw640d 56/56 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replac es all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2004 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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